Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2016-0010200, filed on Jan. 27, 2016,and entitled, “Semiconductor Device and Method of Manufacturing theSame,” is incorporated by reference herein in its entirety.

BACKGROUND

1. Field

One or more embodiments described herein relate to a semiconductordevice and a method for manufacturing a semiconductor device.

2. Description of the Related Art

The demand for improved performance, speed, and functionality hasresulted in an increase in the integration of semiconductor devices. Oneapproach for increasing integration involves reducing the width orseparation distance of interconnect lines. However, this approach asincreased in parasitic capacitance in many cases.

SUMMARY

In accordance with one or more embodiments, a semiconductor deviceincludes an element layer; a plurality of first interconnect lines onthe element layer, the first interconnect lines extending in a firstdirection; a first insulation layer between the first interconnect linesand having a uniform carbon concentration distribution; a plurality ofsecond interconnect lines extending in the first direction and spacedfrom the first interconnect lines in a second direction different fromthe first direction; and a second insulation layer adjacent the secondinterconnect lines, wherein an air gap is between the secondinterconnect lines.

In accordance with one or more other embodiments, a semiconductor deviceincludes a first region including a first plurality of interconnectlayers and a first plurality of insulation layers having a firststructure over a first transistor; a second region including a secondplurality of interconnect layers and a second plurality of insulationlayers having a second structure over a second transistor wherein: thefirst plurality of interconnect layers includes a plurality of firstinterconnect lines and a plurality of second interconnect lines, thefirst plurality of insulation layers includes a first insulation layerand a second insulation layer, the first insulation layer between thefirst interconnect lines and having a uniform carbon concentrationdistribution, the second insulation layer adjacent to the secondinterconnect lines, and a first air gap is between the secondinterconnect lines.

In accordance with one or more other embodiments, a method formanufacturing a semiconductor device includes forming a first insulationlayer having a first opening on a substrate; forming first interconnectlines while filling the first opening with a conductive material;removing at least a portion of the first insulation layer to allowlateral surfaces of the first interconnect lines to be exposed; forminga first dielectric layer covering upper surfaces and lateral surfaces ofthe first interconnect lines; forming a second insulation layer extendedupwardly while filling spacings between the first interconnect lines, onthe first dielectric layer; forming a third insulation layer having asecond opening above the second insulation layer; forming secondinterconnect lines while filling the second opening with a conductivematerial; removing at least a portion of the third insulation layer toallow lateral surfaces of the second interconnect lines to be exposed;and forming a fourth insulation layer having an air spacing, between thesecond interconnect lines.

BRIEF DESCRIPTION OF THE DRAWINGS

Features will become apparent to those of skill in the art by describingin detail exemplary embodiments with reference to the attached drawingsin which:

FIGS. 1A and 1B illustrate an embodiment of a semiconductor device;

FIGS. 2 to 4 illustrate other embodiments of a semiconductor device;

FIG. 5 illustrates an embodiment for determining an insulation layertype;

FIGS. 6A to 6M illustrate an embodiment of a method for manufacturing asemiconductor device;

FIGS. 7A to 7C illustrate views another embodiment of a method formanufacturing a semiconductor device;

FIG. 8 illustrates another embodiment of a semiconductor device;

FIG. 9 illustrates an embodiment of a storage device;

FIG. 10 illustrates an embodiment of an electronic device; and

FIG. 11 illustrates an embodiment of a system.

DETAILED DESCRIPTION

FIGS. 1A and 1B illustrate an embodiment of a semiconductor device 100.FIG. 1A is a layout view of the semiconductor device 100. The layoutview has only one interconnect layer M (e.g., a second interconnectlayer 125) among a plurality of interconnect layers M in FIG. 1B forease of understanding. FIG. 1B illustrates a cross-sectional view of thesemiconductor device 100 taken along line X-X′ in FIG. 1A.

Referring to FIGS. 1A and 1B, the semiconductor device 100 may include asubstrate 101, an element layer 105, first to eighth insulation layers110, 120, 130, 140, 150, 160, 170, and 180 (insulation layers IL), andfirst to eighth interconnect layers 115, 125, 135, 145, 155, 165, 175,and 185 (interconnect layers M). The semiconductor device 100 mayfurther include diffusion barrier layers 112, 122, 132, 142, 152, 162,172, and 182 on lateral surfaces and lower surfaces of the respectiveinterconnect layers M, and first to eighth dielectric layers 118, 128,138, 148, 158, 168, 178, and 188 on upper surfaces of the interconnectlayers M.

The substrate 101 may include a semiconductor material, for example, aGroup IV semiconductor, a Group III-V compound semiconductor, or a GroupII-VI compound semiconductor. The group IV semiconductor may include,for example, silicon, germanium, or silicon-germanium. The substrate 101may be provided as a bulk wafer, an epitaxial layer, asilicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI)layer, or the like.

The element layer 105 may be on the substrate 101 and may include one ormore semiconductor elements. The element layer 105 may include, forexample, a transistor, a lower interconnect, an insulation layer, and/orother elements.

The first to eighth interconnect layers M may be on the element layer105 and may include first to eighth interconnect lines 115 b, 125 b, 135b, 145 b, 155 b, 165 b, 175 b, and 185 b (interconnect lines ML), andfirst to eighth contact plugs 115 a, 125 a, 135 a, 145 a, 155 a, 165 a,175 a, and 185 a (contact plugs MC) connecting upper and lowerinterconnect lines ML to each other, respectively. The interconnectlayers M are illustrated to have a dual damascene structure in which theinterconnect lines ML and the contact plugs MC are integrally formed. Inother embodiments, the interconnect layers M may have a structure inwhich the interconnect lines ML and the contact plugs MC are separatelyformed. In this case, the first to eighth dielectric layers 118, 128,138, 148, 158, 168, 178, and 188 may not have a shape extended alongsurfaces of the interconnect lines ML, as illustrated in FIG. 1B. Inaddition, the number of the interconnect layers M may be different inother embodiments.

The interconnect layers M may be formed, for example, of a lowresistance conductive material such as copper (Cu), tungsten (W), oraluminum (Al). As illustrated in FIG. 1A, each of the interconnect linesML may include interconnect patterns MLa and MLb having a large range ofpitches. A first interconnect pattern MLa may have a first width W1 witha first space S1 and may have a first pitch P1, which corresponds to thesum of the first width W1 and the first space S1.

The second interconnect pattern MLb may have a second width W2 with asecond space S2. The second width W2 may be greater than the first widthW1, and the second space S2 may be equal to or greater than the firstspace S1. The second interconnect pattern MLb may also have a secondpitch P2 which is greater than the first pitch P1 and which correspondsto a sum of the second width S2 and the second space S2. The arrangementof the interconnect lines ML and contact plugs MC and the pitches of theinterconnect lines ML may be different in other embodiments.

Each of the interconnect lines in a lower portion of the semiconductordevice (e.g., the first to fourth interconnect lines 115 b, 125 b, 135b, and 145 b) may have a smaller width than the interconnect lines(e.g., the fifth to eighth interconnect lines 155 b, 165 b, 175 b, and185 b) in an upper portion of the semiconductor device. Also, spacesbetween the lower interconnect lines ML may be smaller than spacesbetween the upper interconnect lines ML. For example, a first distanceD1 (e.g., a minimum distance between the first interconnect lines 115 b)may be less than a second distance D2 (e.g., a minimum distance betweenthe sixth interconnect lines 165 b).

Each of the first, second, sixth, and seventh interconnect lines 115 b,125 b, 165 b, and 175 b may have a relatively higher capacitance ratioto total capacitance of an entirety of the interconnect lines ML than acapacitance ratio of other interconnect lines ML. In addition, the firstand second interconnect lines 115 b and 125 b may include a interconnectpattern with a fine pitch for connecting highly integrated semiconductorelements to include interconnect patterns having a relatively largerrange of pitches.

The sixth and seventh interconnect lines 165 b and 175 b are in arelatively high portion of the semiconductor device and mainly connectspacings between the interconnect layers M. The sixth and seventhinterconnect lines 165 b and 175 b may be formed of interconnectpatterns having a single pitch or may include interconnect patternshaving relatively few types of pitches. The number of contact plugs MCconnected to upper surfaces of the sixth and seventh interconnect lines165 b and 175 b may be less than the number of contact plugs MCconnected to upper surfaces of the first and second interconnect lines115 b and 125 b.

The diffusion barrier layers 112, 122, 132, 142, 152, 162, 172, and 182may surround lower surfaces and lateral surfaces of the interconnectlines ML and the contact plugs MC in respective interconnect layers M.The diffusion barrier layers 112, 122, 132, 142, 152, 162, 172, and 182may be formed of a conductive material, and thus may be classified as aportion of the interconnect layer M.

The diffusion barrier layers 112, 122, 132, 142, 152, 162, 172, and 182may be formed, for example, of at least one of titanium (Ti), titaniumnitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru),cobalt (Co), manganese (Mn), tungsten nitride (WN), nickel (Ni), andnickel boron (NiB).

The respective insulation layers IL may fill spacings between theinterconnect lines ML and the contact plugs MC forming the interconnectlayer M. The insulation layers IL may include a low dielectric constant(low-k) material or an ultra-low dielectric constant (ultra low-k)material having a dielectric constant lower than a predetermined value,e.g., 2.5. The insulation layers IL may be formed, for example, ofhydrogen carbide oxide silicon (SiOCH), porous-hydrogen carbide oxidesilicon (porous-SiOCH), or the like.

One or both of the second and third insulation layers 120 and 130 may bea layer formed by a process different from a process for forming thefourth and fifth insulation layers 140 and 150 and the sixth and seventhinsulation layers 160 and 170. An embodiment of a process for formingthe second and third insulation layers will be described in more detailwith reference to FIGS. 6A to 6L.

Lower layers 120 a and 130 a may be formed in parallel with first andsecond interconnect lines 115 b and 125 b in the second and thirdinsulation layers 120 and 130, and may be formed, for example, of aSpin-on-Dielectric (SOD) material such as tonen silazene (TOSZ).

In addition, the lower layers 120 a and 130 a may be formed of anultra-low dielectric constant material with no carbon-depletion. Thus,the concentration of carbon inside the second and third insulationlayers 120 and 130, which are between adjacent interconnect lines 115 band 125 b, may be uniformly distributed. The capacitance of the secondand third insulation layers 120 and 130 may be reduced, for example, byabout 10% in comparison with an insulation layer including acarbon-deficient region.

At least one of fourth or fifth insulation layers 140 and 150 and aneighth insulation layer 180 may have a carbon-deficient region, in whichthe concentration of carbon inside the insulation layer IL is relativelylow in a region adjacent to the interconnect lines ML, and may havedistribution in which the concentration of carbon is increased whilebeing spaced apart from the interconnect lines ML. In anotherembodiment, the semiconductor device may not include an insulation layerIL having non-uniform distribution of a concentration of carbon.

The sixth and seventh insulation layers 160 and 170 may include lowerlayers 160 a and 170 a and upper layers 160 b and 170 b. The lowerlayers 160 a and 170 a and the upper layers 160 b and 170 b may beformed of the same or different materials.

For example, the upper layers 160 b and 170 b that are parallel to thesixth and seventh interconnect lines 165 b and 175 b may have internalair spacings AG1 and AG2, respectively. The air spacing AG1 may bebetween the adjacent interconnect lines 165 b, and the air spacing AG2may be between the adjacent interconnect lines 175 b. The air spacingsAG1 and AG2 may be in regions spaced apart from the seventh contactplugs 175 a in upper surfaces of the interconnect lines 165 b by a thirddistance D3. The third distance D3 may be different in otherembodiments. In some example embodiments, the air spacings AG1 and AG2may be in contact with the lower layers 160 a and 170 a.

The upper layers 160 b and 170 b may be formed to include the airspacings AG1 and AG2, respectively, for example, by being depositedusing a material having non-conformal deposition characteristics or bycontrolling deposition conditions. The upper layers 160 b and 170 b maybe formed, for example, of tetraethoxysilane (TEOS) or hydrogen carbideoxide silicon (SiOCH). The upper layers 160 b and 170 b may include theair spacings AG1 and AG2 to reduce a parasitic capacitance. In oneembodiment, the air spacings AG1 and AG2 may reduce parasiticcapacitance by about 17%.

In the example embodiment, the insulation layers 120 a and 130 a may beformed of a layer with no carbon-depletion. The insulation layers 160 band 170 b may be formed of a layer having the air spacings AG1 and AG2,which may be determined based on characteristics of interconnect linesML inside respective insulation layers IL.

For example, based on the capacitance of an entirety of the interconnectlines ML, an insulation layer IL, disposed at the same height asinterconnect lines ML having a relatively large capacitance ratio, mayinclude a layer with no carbon-depletion or a layer having an airspacing. In addition, in an area of the entirety of the interconnectlines ML, an insulation layer IL, disposed at the same height asinterconnect lines ML having a relatively low ratio of an area in whichcontact plugs MC are disposed on upper portions of the interconnectlines ML, may include a layer having an air spacing. The number of aninsulation layers IL including a layer with no carbon-depletion and thenumber of insulation layers IL including a layer having an air spacingmay be different for different embodiments.

Thus, according to this example embodiment, the semiconductor deviceincludes a plurality of interconnect layers M and a portion of aninsulation layer IL includes a layer with no carbon-depletion or a layerhaving an air spacing to reduce a dielectric constant. Thus, parasiticcapacitance among the interconnect layers M is reduced, which may causea significant reduction in RC delay and secure or improve one or moreelectrical properties (e.g., operation speed) of the semiconductordevice 100.

The first to eighth dielectric layers 118, 128, 138, 148, 158, 168, 178,and 188 may cover upper surfaces of the interconnect lines ML,respectively. The first to eighth dielectric layers 118, 128, 138, 148,158, 168, 178, and 188 may protect the interconnects ML, may preventdiffusion, or may be used as etch stop layers during manufacturing. Thefirst to eighth dielectric layers 118, 128, 138, 148, 158, 168, 178, and188 may be formed, for example, of silicon carbonitride (SiCN), siliconnitride (SiN), silicon oxycarbide (SiOC), or the like.

The first and second dielectric layers 118 and 128 may be oninterconnect lines 115 b and 125 b to cover not only upper surfaces butalso lateral surfaces of the interconnect lines 115 b and 125 b,respectively. The third to eighth dielectric layers 138, 148, 158, 168,178, and 188 may extend linearly and horizontally to cover uppersurfaces of interconnect lines 135 b, 145 b, 155 b, 165 b, 175 b, and185 b, respectively.

FIGS. 2 to 4 are cross-sectional views illustrating other embodiments ofa semiconductor device. FIG. 2 illustrates an embodiment of asemiconductor device 100 a which may include a substrate 101, an elementlayer 105, insulation layers IL, interconnect layers M, diffusionbarrier layers 112, 122, 132, 142, 152, 162, 172, and 182, and first toeighth dielectric layers 118′, 128′, 138, 148, 158, 168, 178, and 188.

Between first interconnect lines 115 b and between second interconnectlines 125 b, lower surfaces of first and second dielectric layers 118′and 128′ are spaced apart from lower surfaces of first and secondinterconnect lines 115 b and 125 b, respectively by a fourth distanceD4. Thus, in the example embodiment of FIG. 2, the lower surfaces offirst and second dielectric layers 118′ and 128′ are below theinterconnect lines. Therefore, the first and second dielectric layers118′ and 128′ may be between the first interconnects 115 b and betweenthe second interconnect lines 125 b, respectively, in recessed form. Asa result, boundaries of the insulation layers ML in upper and lowerportions of the first and second dielectric layers 118′ and 128′ may bechanged by the first and second dielectric layers 118′ and 128′.

In a similar manner, air spacings AG1′ and AG2′ between the sixthinterconnect lines 165 b and between the seventh interconnect lines 175b may be below lower surfaces of the sixth and seventh interconnectlines 165 b and 175 b, respectively. Thus, in sixth and seventhinsulation layers 160 and 170, boundaries of lower layers 160 a and 170a and upper layers 160 b and 170 b may be lowered.

FIG. 3 illustrates an embodiment of a semiconductor device 100 b whichmay include a substrate 101, an element layer 105, insulation layers IL,interconnect layers M, diffusion barrier layers 112, 122, 132, 142, 152,162, 172, and 182, and first to eighth dielectric layers 118, 128, 138,148, 158, 168, 178, and 188.

Sixth and seventh insulation layers 160′ and 170′ are not on lateralsurfaces of sixth and seventh interconnect lines 165 b and 175 b, butare only be on lower portions of the sixth and seventh interconnectlines 165 b and 175 b, respectively. In this embodiment, the lateralsurfaces of the sixth and seventh interconnect lines 165 b and 175 b mayinclude only air spacings AG1″ and AG2″, respectively. Also, in thisexample embodiment, the thickness D5 of the sixth and seventh dielectriclayers 168 and 178 in upper portions of the air spacings AG1″ and AG2″may be greater than the thickness of the sixth and seventh dielectriclayers in the example embodiment of FIG. 1B.

FIG. 4 illustrates an embodiment of a semiconductor device 100 c whichmay include a substrate 101, an element layer 105, insulation layers IL,interconnect layers M, diffusion barrier layers 112, 122, 132, 142, 152,162, 172, and 182, and first to eighth dielectric layers 118, 128, 138,148, 158, 168, 178, and 188.

Second and third insulation layers 120′ and 130′ may include lowerlayers 120 a and 130 a and upper layers 120 b′ and 130 b′ formed ofmaterials different from each other. The lower layers 120 a and 130 amay be formed of an ultra-low dielectric constant material with nocarbon-depletion in a manner similar to the example embodiment in FIG.1B. The upper layers 120 b′ and 130 b′ may be formed of the samematerial as at least one of fourth, fifth, or eighth insulation layers140, 150, and 180 and in a process different from that used to form thelower layers 120 a and 130 a.

The example embodiments described above with reference to FIGS. 1A to 4,may be combined with each other, or portions thereof may be selected andcombined with each other.

FIG. 5 illustrates an embodiment of a method for determining the type ofinsulation layer in a semiconductor device. The method includes anoperation for determining the structure of respective insulation layersIL to be manufactured, for example, in the embodiment of FIG. 1B.

The structure of the insulation layers IL may be determined as one ofthree structures. A general structure S20 refers to a structure formedof a low dielectric constant or ultra-low dielectric constant materialsuch as the fourth, fifth, and eighth insulation layers 140, 150, and180 in FIG. 1B. According to the general structure S20, the insulationlayer IL may include a carbon-deficient region. The carbon-deficientregion-excluding structure S22 refers to a structure formed of anultra-low dielectric constant material not including a carbon-deficientregion, such as second and third insulation layers 120 and 130. An airspacing-including structure S24 includes air spacings AG1 and AG2, forexample, such as sixth and seventh insulation layers 160 and 170.

The method initially includes determining whether the capacitance ratioof interconnect lines ML inside one insulation layer IL is greater thana critical ratio P1 c (S12). The capacitance ratio may refer to acapacitance ratio of interconnect lines ML of a correspondinginterconnect layer M to a total capacitance of interconnect lines ML ofan entirety of the interconnect layers M. The critical ratio P1 c maybe, for example, 7% to 10% and may be determined based on thedistribution of a capacitance ratio between interconnect layers M, thenumber of interconnect layers M, and/or another parameter.

When the capacitance ratio is less than the critical ratio P1 c (e.g.,when the capacitance due to corresponding interconnect lines ML isrelatively small), the insulation layers may be manufactured to have thegeneral structure S20.

In some example embodiments, operation S12 may be determined by aranking of a capacitance ratio of interconnect layers M, instead ofcritical ratio P1 c. For example, a layer having the lowest capacitanceratio or interconnect lines ML in a lower ranking 40% to 70% may bemanufactured to have the general structure S20. The subsequentdetermination may be carried out with respect to insulation layers ILbetween interconnect lines ML having a relatively high capacitanceratio. For example, interconnect lines ML of a lowermost interconnectlayer M may include a interconnect pattern with a fine pitch forconnection of highly integrated semiconductor elements inside theelement layer 105. Thus, the capacitance ratio may be high.

When the capacitance ratio is equal to or greater than the criticalratio P1 c, the method includes determining whether the ratio of alanding via-excluding region is less than a critical ratio P2 c (S16). Alanding via-excluding region may refer to a region in which interconnectlines ML inside a corresponding insulation layer IL are not connected tocontact plugs MC on upper portions of the interconnect lines ML. Thus,with respect to respective interconnect layers M, the ratio of a landingvia-excluding region may be calculated based on the ratio of an area ofa region in which interconnect lines ML are not connected to contactplugs MC to a total area of the interconnects ML.

In some example embodiments, the landing via-excluding region may becalculated as a region expanded by a predetermined distance from acircumference of contact plugs MC. The critical ratio P2 c may be, forexample, 90% to 98%. In some example embodiments, the critical ratio P2c may be 96%.

In a manner similar to operation S12 described above, because the ratioof a landing via-excluding region may be determined within apredetermined ratio based on a ranking of a ratio instead of criticalratio P2 c in operation S16, the insulation layers may be manufacturedto have the air spacing-including structure S24. In some exampleembodiments, in a manner similar to operation S12 described above,operation S16 may be determined, not based on an area ratio, but basedon a capacitance ratio of a region in which interconnect lines ML arenot connected to contact plugs MC on upper portions of the interconnectlines ML. On the other hand, the determination in operation S16 may becarried out based on a ratio of a landing via region, e.g., a region inwhich interconnect lines ML are connected to contact plugs MC on upperportions of interconnect lines ML.

When a ratio of a landing via-excluding region is less than the criticalratio P2 c, the insulation layers may be manufactured to have acarbon-deficient region-excluding structure S22. When the contact plugsMC are connected to upper portions of interconnect lines ML, an airspacing may not be provided between the interconnect lines ML around alanding via region, in order to prevent formation of a defect.

When the number of interconnect layers M is high, and when acarbon-deficient region-excluding structure S22 or an airspacing-including structure S24 is applied to an entirety of insulationlayers IL, the manufacturing process may be complicated and costs mayincrease. Thus, through a determination operation in the exampleembodiment, a corresponding structure is applied to a portion ofinsulation layers IL to save costs and manufacturing time and toefficiently lower total parasitic capacitance.

Next, when an air spacing-including structure S24 is applied to theinsulation layers, a determination is made as to whether the number ofpitches of interconnect lines ML to which an air spacing is applied isless than a critical number N_(c), in order to determine an air spacingforming process S30. However, operation S30 may be selectively carriedout and may be omitted in some example embodiments.

Interconnect lines ML forming one interconnect layer M may includeinterconnect patterns having one or more pitches different from eachother. When an air spacing is applied to interconnect lines ML, thenumber of pitches which have been applied to interconnect patterns maybe determined, thereby forming air spacings by different processes. Acritical number N_(c) may be, for example, 2 to 4.

When types of pitches to be applied are less than the critical numberN_(c), a first process may be applied (S40). The first process may be,for example, a process for forming an air spacing AG1 in FIG. 1, bydepositing an non-conformal layer as described with reference to FIG.6M.

When the types of pitches to be applied are greater than the criticalnumber N_(c), a second process may be applied (S42). The second processmay be a process for uniformly forming air spacings between allinterconnect patterns, even when the types of pitches vary in comparisonwith the first process. The second process may be, for example, aprocess for forming an air spacing AG1″ in FIG. 3 using a sacrificiallayer 161, as described with reference to FIGS. 7A to 7C.

FIGS. 6A to 6M illustrate a process sequence for an embodiment of amethod for manufacturing a semiconductor device. Referring to FIG. 6A,an element layer 105 is formed on a substrate 101. This may involveforming one or more semiconductor elements (e.g., transistor(s)) andthen an insulation layer on an upper portion of the element layer. Theinsulation layer is then planarized to form the element layer 105.

Then, a first preliminary insulation layer 110P having first openingsOP1 are formed on the element layer 105. The may involve depositing aninsulation material on element layer 105 and then etching a portion ofthe insulation material to form the first preliminary insulation layer110P. A portion of the first preliminary insulation layer may form afirst insulation layer 110 through a subsequent process.

The first preliminary insulation layer 110P may be formed of a lowdielectric constant or ultra-low dielectric constant material such ashydrogen carbide oxide silicon (SiOCH) or porous-hydrogen carbide oxidesilicon (porous-SiOCH). The first preliminary insulation layer 110P maybe formed by a process such as chemical vapor deposition (CVD), lowpressure chemical vapor deposition (LPCVD), plasma enhanced chemicalvapor deposition (PECVD), high density plasma-chemical vapor deposition(HDP-CVD), a spin coating process, or the like.

Through the subsequent process, lower regions of the first openings OP1may form areas for contact plugs MC and upper regions of the firstopenings OP1 may form areas for interconnect lines ML (see, e.g., FIGS.1A and 1B). Using a additional mask layer, upper regions of the firstopenings OP1 may be formed to be linear after the lower regions in theform of holes are formed in advance, or the lower regions may be formedas a hole after upper regions having a linear form are formed inadvance.

Referring to FIG. 6B, diffusion barrier layers 112 and firstinterconnect layers 115 may be sequentially formed inside the firstopenings OP1 of the first preliminary insulation layer 110P. After amaterial forming the diffusion barrier layers 112 and the firstinterconnect layers 115 is deposited, a planarization process (e.g.,chemical mechanical polishing (CMP)) may be performed to form thediffusion barrier layers 112 and the first interconnect layers 115inside the first openings OP1.

The diffusion barrier layers 112 may prevent metallic material formingthe first interconnect layers 115 from diffusing into the firstinsulation layers 110 (see, e.g., FIG. 1B). The diffusion barrier layers112 may be formed, for example, of metal or a metal nitride such as butnot limited to titanium (Ti), a titanium nitride (TiN), tantalum (Ta), atantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn),tungsten nitride layer (WN), nickel (Ni), and nickel boron (NiB). Thefirst interconnect layers 115 may be formed of a metallic material suchas copper (Cu), aluminum (Al), titanium (Ti), or tungsten (W).

The diffusion barrier layers 112 and the first interconnect layers 115may be formed to be conformal along lateral walls of the firstpreliminary insulation layers 110P and exposed through the firstopenings OP1. The diffusion barrier layers 112 and the firstinterconnect layers 115 may be formed, for example, through physicalvapor deposition (PVD), a sputtering process, or an atomic layerdeposition (ALD) process.

The first preliminary insulation layer 110P around the first openingsOP1 may be subject to plasma-induced damage by an etching process whenthe first openings OP1 are formed and a process of forming the diffusionbarrier layers 112. Thus, when the first preliminary insulation layers110P are a carbon-containing film, a carbon-deficient region may beformed around the first openings OP1. As interconnect lines 115 b areformed more densely than contact plugs 115 a, the carbon-deficientregion may be generated to a greater extent in upper regions of thefirst preliminary insulation layers 110P, in comparison with the lowerregions.

Referring to FIG. 6C, upper portions of the first preliminary insulationlayers 110P are partially removed to form the first insulation layers110. A portion of the first preliminary insulation layer 110Pcorresponding, for example, to a sixth length D6 may be removed from anupper surface using an etch-back process. In example embodiments, thesixth length D6 may be different in other embodiments. By the process inFIG. 6C, portions of the first preliminary insulation layers 110Pbetween the first interconnect lines 115 b having a carbon-deficientregion may be removed. Thus, the first insulation layers 110 may beformed without a further photolithographic process.

In a case of the example embodiment in FIG. 2, the first insulationlayers may be manufactured by removing portions below lower portions ofthe first interconnect lines 115 b, of the first preliminary insulationlayers 110P in the process of FIG. 6C.

In some example embodiments, before a process of removing portions ofthe first preliminary insulation layers 110P, protective layersincluding metal, a metal oxide film, or a metal nitride film may beformed on upper surfaces of the first interconnect lines 115 b.

Referring to FIG. 6D, the method further includes forming a firstdielectric layer 118 covering upper surfaces of the first insulationlayers 110 and upper surfaces and lateral surfaces of the firstinterconnect lines 115 b. The first dielectric layer 118 may be a layerprotecting the first interconnect lines 115 b from moisture, oxygen, orthe like, and may serve to prevent diffusion. The first dielectric layer118 may be formed, for example, of silicon carbonitride (SiCN), siliconnitride (SiN), silicon oxycarbide (SiOC), or the like. The firstdielectric layer 118 may be formed by CVD, ALD, or the like.

Referring to FIG. 6E, a second preliminary insulation layer 120P may beformed on the first dielectric layer 118. The second preliminaryinsulation layer 120P may be formed of an ultra-low dielectric constantmaterial and, for example, a silicon carbide-based SOD material. Thesecond preliminary insulation layer 120P may be formed, for example, bya spin-coating process, a flowable chemical vapor deposition (CVD)process, or another process. After the second preliminary insulationlayer 120P is deposited, a heat treatment or UV treatment process may beperformed.

The second preliminary insulation layer 120P may fill spacings betweenthe first interconnect lines 115 b and may be formed upwardly. Thesecond preliminary insulation layer 120P may be formed to a heightcorresponding, for example, to a seventh length D7 from the firstdielectric layer 118. The seventh length D7 may be substantially thesame as the height from the first dielectric layer 118 to upper surfacesof second interconnect layers 125 (see, e.g., FIG. 1B) on an upperportion of the second preliminary insulation layer.

In the case of the example embodiment in FIG. 4, a second insulationlayer 120 (see, e.g., FIG. 1B) may be manufactured by forming the secondpreliminary insulation layer at a height to fill spacings between thefirst interconnect lines 115 b in the process of FIG. 6E.

Referring to FIG. 6F, second openings OP2 may be formed inside thesecond preliminary insulation layer 120P. The second openings OP2 may beformed, for example, by a process similar to the process for forming thefirst opening OP1 described above. The second openings OP2 may be formedto allow the first interconnect lines 115 b in lower portions of thesecond openings to be recessed to a predetermined depth, or uppersurfaces of the first interconnect lines 115 b to be exposed.

Referring to FIG. 6G, diffusion barrier layers 122 and secondinterconnect layers 125 may be sequentially formed inside the secondopenings OP2 of the second preliminary insulation layer 120P. Theprocess illustrated in FIG. 6G may be performed, for example, in amanner similar to the method with reference to FIG. 6B.

After materials forming the diffusion barrier layers 122 and the secondinterconnect layers 125 are deposited, a planarization process may beperformed. The diffusion barrier layers 122 may prevent metallicmaterial forming the second interconnect layers 125 from diffusing tothe second insulation layer 120 (see, e.g., FIG. 1B).

The second preliminary insulation layer 120P around the second openingsOP2 may be subject to plasma-induced damage by an etching process whenthe second openings OP2 are formed and a process for forming thediffusion barrier layers 122 is performed in FIG. 6G. Thus, when theinsulation layer 120P is a carbon-containing film, a carbon-deficientregion may be formed around the second openings OP2. For example, thecarbon-deficient region may be generated to a greater extent in upperregions of the second preliminary insulation layer 120P disposed onlateral surfaces of the second interconnect lines 125 b, in comparisonwith lower regions of the second preliminary insulation layer 120P.

FIG. 6G illustrates the second preliminary insulation layer 120P dividedinto an upper layer 120Pb and a lower layer 120Pa. The upper layer 120Pbis between the second interconnect layers 125 in which etching anddepositing processes are performed. The lower layer 120Pa between thefirst interconnect lines 115 b is not damaged by such processes.

Referring to FIG. 6H, upper portions of the second preliminaryinsulation layer 120P are partially removed to form a second insulationlayer 120 and to form a second dielectric layer 128 above the secondinsulation layer. The process illustrated in FIG. 6H may be performed,for example, in a manner similar to the method in FIGS. 6C and 6D.

Upper portions of the second preliminary insulation layer 120P, forexample, may be partially removed using an etch-back process. Thus,portions of the second preliminary insulation layer 120P between thesecond interconnect lines 125 b having a carbon-deficient region may bepartially removed. A lower layer 120 a of the second insulation layer120 between the first interconnect lines 115 b may be a layer notdamaged by etching and depositing. In the cause of the exampleembodiment of FIG. 2, the second insulation layer may be manufactured byremoving the second preliminary insulation layer 120P to lower portionsof the second interconnect lines 125 b in the process of FIG. 6H.

The second dielectric layer 128 may protect the second interconnectlines 125 b from an external environment and may serve to preventdiffusion.

Referring to FIG. 6I, a third preliminary insulation layer 130P may beformed on the second dielectric layer 128. The process in FIG. 6I may beperformed, for example, in a manner similar to the method of FIGS. 6Cand 6D.

The third preliminary insulation layer 130P may fill spacings betweenthe second interconnect lines 125 b and may be formed upwardly. An uppersurface level of the third preliminary insulation layer 130P may besubstantially the same as upper surface levels of third interconnectlayers 135 (see, e.g., FIG. 1B). In the case of the example embodimentin FIG. 4, a third insulation layer 130 (see, e.g., FIG. 1B) may bemanufactured by forming the third preliminary insulation layer to aheight sufficient to fill spacings of the second interconnect lines 125b in the process of FIG. 6I.

Referring to FIG. 6J, after the third interconnect layer 135 is formedinside the third preliminary insulation layer 130P, a third dielectriclayer 138 may be formed thereon. The processes described in FIGS. 6F and6G may be repeatedly performed to form the third insulation layer 130and the third interconnect layer 135.

The third dielectric layer 138 may be formed to extend horizontally tocover upper surfaces of the third insulation layer 130 and the thirdinterconnect layers 135. The third dielectric layer 138 may be formed ofa material which is the same as or different from a material of thefirst and second dielectric layers 118 and 128. The third dielectriclayer 138 may perform a diffusion prevention function and an etch stopfunction.

Referring to FIG. 6K, fourth and fifth insulation layers 140 and 150, asixth preliminary insulation layer 160P, and fourth to sixthinterconnect layers 145, 155, and 165 may be formed on the thirddielectric layer 138.

After the respective fourth and fifth insulation layers 140 and 150including openings and the sixth preliminary insulation layer 160P areformed, the openings are filled with conductive material to form thefourth to sixth interconnect layers 145, 155, and 165. Diffusion barrierlayers 142, 152, and 162 may be formed on lower surfaces and lateralsurfaces of the fourth to sixth interconnect layers 145, 155, and 165.Fourth and fifth dielectric layers 148 and 158 may be formed on uppersurfaces of the fourth and fifth interconnect layers 145 and 155.

At least a partial region of the fourth and fifth insulation layers 140and 150 and the sixth preliminary insulation layer 160P may be damagedduring an process of forming the fourth to sixth interconnect layers145, 155, and 165. Thus, carbon-deficiency may occur in a regionadjacent to the fourth to sixth interconnect layers 145, 155, and 165.In some example embodiments, the fourth and fifth insulation layers 140and 150, and the sixth preliminary insulation layer 160P may be formedof a material different from a material of the second and thirdinsulation layers 120 and 130, and thus may not include acarbon-deficient region.

Referring to FIG. 6L, upper portions of the sixth preliminary insulationlayer 160P are partially removed to form a lower layer 160 a of a sixthinsulation layer 160.

Before the sixth preliminary insulation layer 160P is removed, a masklayer may be formed by a photolithographic process. The mask layer maybe patterned so as not to allow a region corresponding to a via landingregion to be exposed, e.g., a region in which seventh contact plugs 175a (see, e.g., FIG. 1B) are disposed on upper portions of the mask layer.Upper portions of the sixth preliminary insulation layer 160P may bepartially removed using an etching process. By the process in FIG. 6L,the sixth preliminary insulation layer 160P between the sixthinterconnect lines 165 b including a carbon-deficient region may beremoved.

In a case of the example embodiment in FIG. 2, the sixth insulationlayer may be manufactured by removing the sixth preliminary insulationlayer 160P to lower portions of the sixth interconnect lines 165 b inthe process in FIG. 6L.

In some example embodiments, before a process of removing the sixthpreliminary insulation layer 160P is performed, a protective layer ofmetal, a metal oxide film, or a metal nitride film may be formed onupper surfaces of the sixth interconnect lines 165 b.

Referring to FIG. 6M, an upper layer 160 b of the sixth insulation layer160 may be provided between the sixth interconnect lines 165 b. Theupper layer 160 b may be deposited not to be conformal and to have anair spacing AG1 therein. The air spacing AG1 may be in the form of anair tunnel extending in one direction along the sixth interconnect lines165 b.

The upper layer 160 b may be formed using a sputtering or PVD process inwhich step coverage characteristics are not good. Thus, the upper layermay be relatively thickly formed in upper surfaces of the sixthinterconnect lines 165 b and may be relatively thinly formed in lateralsurfaces of the sixth interconnect lines 165 b and upper surfaces of thelower layer 160 a.

The upper layer 160 b may have the air spacing AG1, and thus may beformed as a low dielectric constant layer. This may reduce parasiticcapacitance between the sixth interconnect lines 165 b.

Next, a planarization process is performed to allow upper surfaces ofthe sixth interconnect lines 165 b to be exposed, thereby removingportions of the upper layer 160 b.

With reference also to FIG. 1B, the processes described above may berepeatedly performed to form a seventh insulation layer 170 having anair spacing AG2 and seventh interconnect layers 175. Finally, an eighthinsulation layer 180 and eighth interconnect layers 185 may be formed ina manner similar to the method of forming the fourth and fifthinsulation layers 140 and 150 and fourth and fifth interconnect layers145 and 155 in order to manufacture the semiconductor device 100 in FIG.1B.

FIGS. 7A to 7C illustrate a process sequence of another embodiment of amethod for manufacturing a semiconductor device. In an exampleembodiment, a method of manufacturing a semiconductor device 100 b inFIG. 3 will be described, and descriptions in common with FIGS. 6A to 6Mwill be omitted.

With reference to FIG. 7A, the method initially includes forming firstto fifth interconnect layers 115, 125, 135, 145, and 155. Then, a sixthinsulation layer 160′ and a sacrificial layer 161 may be sequentiallyformed thereon. The first to fifth interconnect layers 115, 125, 135,145, and 155 may be formed, for example, in the same manner as describedabove with reference to FIGS. 6A to 6K.

Next, a sixth insulation layer 160′ and a sacrificial layer 161 may beformed above a fifth dielectric layer 158. The sacrificial layer 161 maybe formed of material having a chemical structure which may be easilymodified by a plasma treatment or a UV treatment. For example, thesacrificial layer 161 may be formed of a silicon oxide-based materialcontaining a hydrocarbon group such as an alkyl group. In oneembodiment, the sacrificial layer 161 may be formed, for example, of aUV decomposition material such as polyketoester, polyketoamide, or thelike. The sacrificial layer 161 may be formed using a process of CVD,PVD, spin coating, or the like.

Referring to FIG. 7B, after a sixth dielectric layer 168 is formed onthe sacrificial layer 161, a process for treating the sacrificial layer161 may be performed. The sixth dielectric layer 168 may be formed of astable material for a plasma or UV treatment in the process in FIG. 7B,and may be more thickly formed than the first to fifth dielectric layers118, 128, 138, 148, and 158 as described with reference to FIG. 3. Insome example embodiments, a capping layer may be formed instead of thesixth dielectric layer 168.

The sacrificial layer 161 may be modified through plasma treatment or UVirradiation. For example, when using a plasma treatment, a gas isinjected into a chamber, and thus, plasma is formed to thereby modifythe sacrificial layer 161 by plasma-induced damage. For example, whenusing a UV treatment, the sacrificial layer 161 may be decomposed byirradiated UV light.

Referring to FIG. 7C, a portion of the modified sacrificial layer 161 isselectively removed to form an air spacing AG1″. The portion of themodified sacrificial layer 161 may be decomposed in the treatingprocess, and thus removed or selectively removed using a separate wetetching process, or the like. Thus, a region between the sixthinterconnect lines 165 b may have the air spacing AG1″.

Next, referring to FIG. 3, a seventh insulation layer 170′ having an airspacing AG2″ and seventh interconnect layers 175 may be formed byrepeatedly performing the process described above.

FIG. 8 is a cross-sectional view illustrating another embodiment of asemiconductor device 200. Referring to FIG. 8, the semiconductor device200 may include first and second regions A and B. The first region A mayinclude transistors having a first length L1 and the second region B maybe a region including transistors having a second length L2 greater thanthe first length L1. The first and second lengths may be channel lengthsof the transistors. In one embodiment, the first region A may be aprocessor region of the semiconductor device 200 and the second region Bmay be a memory region or an input and output circuit region.

The semiconductor device 200 may include an active region 205 inside thesubstrate 101, an element isolation region 203, first and secondelements T and Ta on the substrate 101, and lower interconnect layers211 and 212.

Each of the first and second elements T and Ta may respectively includegate insulation layers 206 and 206 a, gate electrodes 207 and 207 a, andspacers 208 and 208 a. Source/drain regions 209 and 209 a may be onsides of respective ones of the first and second elements T and Ta. Thesource/drain regions 209 of the first elements T may have an elevatedsource/drain form. The first elements T may be, for example, a FinFETelement. The source/drain regions 209 a of the second elements Ta may beinside the substrate 101.

An element insulation layer 210 may be on the first and second elementsT and Ta. Each of the lower interconnect layers 211 and 212 may passthrough the element insulation layer 210 and may be connected to thegate insulation layers 206 and 206 a or the source/drain regions 209 and209 a, respectively.

A plurality of interconnect layers M may be above the lower interconnectlayers 211 and 212. The interconnect layers M and insulation layers ILmay have the same structures, for example, as in FIG. 1B and may be inthe first region A. The interconnect layers M and insulation layers ILmay have the structures described with reference to FIGS. 2 to 4disposed therein.

The interconnect layers M and insulation layers IL in second region Bmay have structures different from the interconnect layers M andinsulation layers IL in the first region A. For example, the secondregion B may include first to third insulation layers 110′, 120″, and130″ different from insulation layers in the first region A. In thesecond region B, the insulation layers IL may not have acarbon-deficient region-excluding structure S22 (see, e.g., FIG. 5).However, the first and second insulation layers 110′ and 120″ in lowerportions of the semiconductor device may have air spacings AG3 and AG4.The third insulation layer 130″ may be formed to have the generalstructure S20 (see, e.g., FIG. 5).

As in the example embodiment, when the semiconductor device 200 isformed of regions including elements T and Ta having sizes differentfrom each other, structures of insulation layers IL between interconnectlayers M may be formed to be different from each other in each region.When sizes of the elements T and Ta are relatively large and arelatively large number of interconnect lines ML having a single pitchare provided, an air spacing-including structure S24 (see, e.g., FIG. 5)may be applied to insulation layers IL in a lower portion of thesemiconductor device. Arrangements of the insulation layers IL inregions different from each other may be variously changed in exampleembodiments.

FIG. 9 illustrates an embodiment of a storage device 1000 which includesa semiconductor device according to any of the aforementionedembodiments. With reference to FIG. 9, the storage device 1000 includesa controller 1010 for communicating with a host and memories 1020-1,1020-2, and 1020-3 for storing data. Each of the controller 1010 and thememories 1020-1, 1020-2, or 1020-3 may include the semiconductor deviceaccording to one or more of the aforementioned embodiments.

The host communicating with the controller 1010 may be, for example, asmartphone, a digital camera, a desktop computer, a laptop computer, aportable media player, or another device. The controller 1010 may storedata on the memories 1020-1, 1020-2, and 1020-3 or generate a commandCMD for retrieving data from the memories 1020-1, 1020-2, and 1020-3 byreceiving a data writing or reading request transmitted from the host.

As illustrated in FIG. 9, one or more memories 1020-1, 1020-2, and1020-3 may be connected to the controller 1010 in parallel to each otherinside the storage device 1000. Because a plurality of memories 1020-1,1020-2, and 1020-3 are connected to the controller 1010 in parallel, thestorage device 1000 may be implemented as a large capacity, e.g., asolid state drive (SSD).

FIG. 10 illustrates an embodiment of an electronic device 2000 whichincludes a semiconductor device according to any of the aforementionedembodiments. Referring to FIG. 10, the electronic device 2000 includes acommunications unit 2010, an input unit 2020, an output unit 2030, amemory 2040, and a processor 2050.

The communications unit 2010 may include a wired/wireless communicationsmodule, a wireless Internet module, a local area communications module,a GPS module, a mobile communications module, and/or the like. Thewired/wireless communications module in the communications unit 2010 maybe connected to an external communications network to transmit andreceive data using various communications standards.

The input unit 2020 allows a user to control operations of theelectronic device 2000. For example, the input unit 2020 may include amechanical switch, a touch screen, a voice recognition module, and thelike. In addition, the input unit 2020 may include a mouse operated in amanner of a track ball, a laser pointer or the like, or a finger mousedevice. In one embodiment, the input unit 2020 may include varioussensor modules to allow a user to input data therewith.

The output unit 2030 may output information processed by the electronicdevice 2000 in the form of audio or video. The memory 2040 may store aprogram for processing and controlling the processor 2050, data, or thelike therein. The processor 2050 may transmit a command to the memory2040 according to required operations to thus store or retrieve data.

The memory 2040 may be embedded in the electronic device 2000 or maycommunicate with the processor 2050 through a separate interface. Whenthe memory communicates with the processor 2050 through the separateinterface, the processor 2050 may store or retrieve data in or from thememory 2040 through various interface standards such as SD, SDHC, SDXC,MICRO SD, USB, and the like.

The processor 2050 may control operations of respective portions in theelectronic device 2000. The processor 2050 may perform controlling andprocessing related to voice calls, video calls, data communications, andthe like, or may perform controlling and processing to multimediaplayback and management. In addition, the processor 2050 may processinput transmitted through the input unit 2020 by a user, and may outputa result thereof through the output unit 2030. In addition, as describedabove, the processor 2050 may store data required for controllingoperations of the electronic device 2000 in the memory 2040, or mayretrieve data required therefor from the memory 2040. At least one ofthe processor 2050 and the memory 2040 may include the semiconductordevice according to various example embodiments of the present inventiveconcept described above with reference to FIGS. 1 to 4, and FIG. 8.

FIG. 11 illustrates an embodiment of a system 3000 which includes asemiconductor device according to one or more of the aforementionedexample embodiments. Referring to FIG. 11, the system 3000 may include acontroller 3100, an input/output device 3200, a memory 3300, and aninterface 3400. The system 3000 may be a mobile system or a systemtransmitting or receiving information. The mobile system may be a PDA, aportable computer, a web tablet, a wireless phone, a mobile phone, adigital music player or a memory card.

The controller 3100 may serve to execute a program and control thesystem 3000. The controller 3100 may be, for example, a microprocessor,a digital signal processor, a microcontroller, or a device similarthereto.

The input/output device 3200 may be used to input or output data of thesystem 3000. The system 3000 may be connected to an external device, forexample, a personal computer or a network using the input/output device3200, to exchange data with the external device. The input/output device3200 may be, for example, a keypad, a keyboard, or a display device.

The memory 3300 may store a code and/or data for operations of thecontroller 3100 therein, or may store data processed in the controller3100. The memory 3300 may include a semiconductor device according toone of example embodiments of the present inventive concept.

The interface 3400 may be a data transmission path between the system3000 and other external device. The controller 3100, the input/outputdevice 3200, the memory 3300, and the interface 3400 may communicatewith each other through a bus 3500. At least one of the controller 3100or the memory 3300 may include a semiconductor device according to anyof the aforementioned example embodiments described with reference toFIGS. 1 to 4, and FIG. 8.

As set forth above, according to example embodiments, differentinterconnect layers in a semiconductor device may respectively includean ultra-low dielectric constant material without a carbon-deficientregion and an air spacing. Thus, a semiconductor device with improvedelectrical properties and reliability may be provided, along with amethod of manufacturing for manufacturing such a device.

Example embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation. Theembodiments may be combined to form additional embodiments. In someinstances, as would be apparent to one of skill in the art as of thefiling of the present application, features, characteristics, and/orelements described in connection with a particular embodiment may beused singly or in combination with features, characteristics, and/orelements described in connection with other embodiments unless otherwiseindicated. Accordingly, it will be understood by those of skill in theart that various changes in form and details may be made withoutdeparting from the spirit and scope of the embodiments set forth in theclaims.

1. A semiconductor device, comprising: an element layer; a plurality offirst interconnect lines on the element layer, the first interconnectlines extending in a first direction; a first insulation layer betweenthe first interconnect lines and having a uniform carbon concentrationdistribution; a plurality of second interconnect lines extending in thefirst direction and spaced from the first interconnect lines in a seconddirection different from the first direction; and a second insulationlayer adjacent the second interconnect lines, wherein an air gap isbetween the second interconnect lines.
 2. The device as claimed in claim1, wherein the second insulation layer is between the secondinterconnect lines and includes the air gap.
 3. The device as claimed inclaim 2, wherein a width of the air gap is less than a spacing betweenthe second interconnect lines.
 4. The device as claimed in claim 2,wherein a width of the air gap is substantially equal to a spacingbetween the second interconnect lines.
 5. The device as claimed in claim1, further comprising: a plurality of third interconnect lines betweenthe first interconnect lines and the second interconnect lines; and athird insulation layer between the third interconnect lines and having anon-uniform carbon concentration distribution.
 6. The device as claimedin claim 1, wherein: the first interconnect lines are separated by afirst spacing, and the second interconnect lines are separated by asecond spacing different from the first spacing.
 7. The device asclaimed in claim 6, wherein the first spacing is less than the secondspacing.
 8. The device as claimed in claim 1, further comprising: afirst number of contact plugs coupled to respective ones of the firstinterconnect lines; and a second number of contact plugs coupled torespective ones of the second interconnect lines, wherein the firstnumber is greater than the second number.
 9. The device as claimed inclaim 1, wherein the first insulation layer has a lower surface belowlower surfaces of the first interconnect lines.
 10. The device asclaimed in claim 9, further comprising: a first dielectric layer betweenthe first insulation layer and the first interconnect lines, wherein alower surface of the first dielectric layer is below the lower surfacesof the first interconnect lines.
 11. The device as claimed in claim 1,wherein the second insulation layer has a lower surface below lowersurfaces of the second interconnect lines.
 12. (canceled)
 13. The deviceas claimed in claim 1, wherein: each of the second interconnect linesincludes a first portion and a second portion, and the second insulationlayer is adjacent to the first portion and is not adjacent to the secondportion.
 14. The device as claimed in claim 13, wherein the air gap isadjacent to the second portion of the second interconnect lines.
 15. Thedevice as claimed in claim 1, wherein: the first insulation layerincludes a first portion and a second portion, and the first and secondportions include different materials.
 16. The semiconductor device asclaimed in claim 1, wherein: the first interconnect lines have a firstpitch, and the second interconnect lines have a second pitch differentfrom the first pitch.
 17. A semiconductor device, comprising: a firstregion including a first plurality of interconnect layers and a firstplurality of insulation layers having a first structure over a firsttransistor; and a second region including a second plurality ofinterconnect layers and a second plurality of insulation layers having asecond structure over a second transistor wherein: the first pluralityof interconnect layers includes a plurality of first interconnect linesand a plurality of second interconnect lines, the first plurality ofinsulation layers includes a first insulation layer and a secondinsulation layer, the first insulation layer between the firstinterconnect lines and having a uniform carbon concentrationdistribution, the second insulation layer adjacent to the secondinterconnect lines, and a first air gap is between the secondinterconnect lines.
 18. The semiconductor device as claimed in claim 17,wherein the first transistor has a first channel length and the secondtransistor has a second channel length different from the first channellength and wherein the first structure is different from the secondstructure.
 19. The device as claimed in claim 17, wherein: the secondplurality of interconnect layers includes a plurality of thirdinterconnect lines and a plurality of fourth interconnect lines, thesecond plurality of insulation layers includes a third insulation layerand a fourth insulation layer, the third insulation layer adjacent tothe third interconnect lines and the fourth insulation layer adjacent tothe fourth interconnect lines, a second air gap is between the fourthinterconnect lines.
 20. The semiconductor device as claimed in claim 19,further comprising: a third air gap is between the third interconnectlines.
 21. The device as claimed in claim 17, wherein: the first regionincludes a processor region, and the second region includes a memoryregion. 22-27. (canceled)